发明授权
US07885367B2 System for adjusting sampling timing of DLL circuit, method therefor and transmitter-receiver used therefor 失效
用于调整DLL电路的采样定时的系统,其方法和用于其的发射机 - 接收机

  • 专利标题: System for adjusting sampling timing of DLL circuit, method therefor and transmitter-receiver used therefor
  • 专利标题(中): 用于调整DLL电路的采样定时的系统,其方法和用于其的发射机 - 接收机
  • 申请号: US11345498
    申请日: 2006-02-02
  • 公开(公告)号: US07885367B2
    公开(公告)日: 2011-02-08
  • 发明人: Takahiro Nishimura
  • 申请人: Takahiro Nishimura
  • 申请人地址: JP Tokyo
  • 专利权人: NEC Corporation
  • 当前专利权人: NEC Corporation
  • 当前专利权人地址: JP Tokyo
  • 代理机构: Sughrue Mion, PLLC
  • 优先权: JP2005-032404 20050209
  • 主分类号: H03D3/22
  • IPC分类号: H03D3/22 H04L27/22
System for adjusting sampling timing of DLL circuit, method therefor and transmitter-receiver used therefor
摘要:
An object of the present invention is to provide a DLL circuit adjustment system that can adjust the sampling timing of a DLL circuit without causing any increase of the number of interface signals or amount of coding overhead and any reduction of the data transfer efficiency. On a transmitter side, an ECC generating section adds an error detection/correction code to transmission data and outputs the transmission data with the error detection/correction code. Of output channels of the transmission data from the ECC generating section, a data bit associated with the DLL circuit to be adjusted is replaced with a sampling timing adjustment pattern using a to-be-adjusted channel selection circuit and a selector, and the resulting transmission data is transmitted to a receiver side. On the receiver side, the transmission data is received via a DLL circuit provided for each channel of the received transmission data, and an error detecting/correcting section corrects any error in the output of each DLL circuit, thereby forming received data. In this way, normal data transfer can be maintained while adjusting the sampling timing of each DLL circuit.
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