Video processing architectures, systems, and methods for a multipoint control unit are provided. In one example, a video processing system includes a motherboard and at least one daughterboard, each daughterboard having a plurality of processors interconnected via a daughterboard switch, where the daughterboard switch is configured to switch data between the plurality of processors and between the motherboard and daughterboard. The video processing system may further include a plurality of daughterboards each having an identical hardware and/or mechanical configuration. The plurality of daughterboards may be configured to be mechanically and electrically couplable together in any order, and may be stackable to form a series chain of daughterboards extending from the motherboard, each respective daughterboard switch being further configured to switch data to a daughterboard switch on another daughterboard to permit data flow along said series chain.