Return path clocking mechanism for a system including a master device connected to a plurality of slave devices via a bus. The master device may first generate a global clock. The master device may transmit data to one or more of the slave devices at a rate of one bit per clock cycle. One or more of the slave devices may transmit data to the master device at a rate of one bit per two consecutive clock cycles. The master device may sample the transmitted data on the second cycle of each two consecutive clock cycle period. Alternatively, the slave devices may transmit data to the master device at a rate of one bit per N consecutive clock cycles, where N≧2, and the master device may sample the transmitted data on the Nth cycle of each N consecutive clock cycle period.