发明授权
US07894151B2 “Flat analog” AFE coupled with an all digital architecture compensation read channel 失效
“平面模拟”AFE加上全数字体系结构补偿读通道

  • 专利标题: “Flat analog” AFE coupled with an all digital architecture compensation read channel
  • 专利标题(中): “平面模拟”AFE加上全数字体系结构补偿读通道
  • 申请号: US12032137
    申请日: 2008-02-15
  • 公开(公告)号: US07894151B2
    公开(公告)日: 2011-02-22
  • 发明人: William Gene Bliss
  • 申请人: William Gene Bliss
  • 申请人地址: US CA Irvine
  • 专利权人: Broadcom Corporation
  • 当前专利权人: Broadcom Corporation
  • 当前专利权人地址: US CA Irvine
  • 代理机构: Garlick Harrison & Markison
  • 代理商 Bruce E. Garlick
  • 主分类号: G11B5/09
  • IPC分类号: G11B5/09
“Flat analog” AFE coupled with an all digital architecture compensation read channel
摘要:
Reading data from a magnetic storage media with an analog front end (AFE) coupled to an all digital read channel compensation architecture. A read head passes over magnetic storage media to produce an analog signal. The analog signal is amplified such that the range of the amplified analog signal substantial matches a range of the analog to digital converter (ADC) used to sample the analog signal. A baseline adjust is performed on the amplified analog signal to center the amplified analog signal to a midscale of the ADC. The amplified analog signal may be sampled where the sampling is data frequency locked by a data lock clock (DLC) tracking module. A digital signal may then be produced from the amplified analog signal where this signal is read channel compensated in the digital domain to produce a digital signal which is then processed with a sequence detector.
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