发明授权
US07895552B1 Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction
有权
提取，可视化和对电路设计与其抽象之间的不一致行为
- 专利标题： Extracting, visualizing, and acting on inconsistencies between a circuit design and its abstraction
- 专利标题（中）： 提取，可视化和对电路设计与其抽象之间的不一致行为
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申请号： US11092994申请日： 2005-03-28
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公开(公告)号： US07895552B1公开(公告)日： 2011-02-22
- 发明人: Vigyan Singhal , Soe Myint , Chung-Wah Norris Ip , Howard Wong-Toi
- 申请人： Vigyan Singhal , Soe Myint , Chung-Wah Norris Ip , Howard Wong-Toi
- 申请人地址： US CA Mountain View
- 专利权人： Jasper Design Automation, Inc.
- 当前专利权人： Jasper Design Automation, Inc.
- 当前专利权人地址： US CA Mountain View
- 代理机构： Fenwick & West LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
In the field of functional verification of digital designs in systems that use an abstraction for portions of a circuit design to perform the verification proof, a tool is described for resolving inconsistencies between the design and abstractions for the design. The tool provides information to a user about intermediate steps in the verification process. In response, the user may provide insight about the design to allow the tool to adjust the verification analysis of the design. The information provided to the user, including possible conflicts between the design and its abstractions, may include visualization techniques to facilitate the user's understating of any inconsistencies.
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