Invention Grant
- Patent Title: Method to produce an electrical model of an integrated circuit substrate and related system and article of manufacture
- Patent Title (中): 制造集成电路基板及相关系统及制品的电气模型的方法
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Application No.: US11769675Application Date: 2007-06-27
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Publication No.: US07900166B2Publication Date: 2011-03-01
- Inventor: Vinod Kariat , Xiaopeng Dong , David Noice
- Applicant: Vinod Kariat , Xiaopeng Dong , David Noice
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Schwegman, Lundberg & Woessner, P.A.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/45
Abstract:
A method is provided to produce a model of an integrated circuit substrate, the method comprising: providing a tile definition that specifies an electrical model associated with instances of the tile; mapping a plurality of respective tile instances to respective locations of the substrate; and connecting the mapped tile instances to each other to produce a tile grid that models overall electrical behavior of the substrate.
Public/Granted literature
- US20090006065A1 METHOD TO PRODUCE SUBSTRATE NOISE MODEL AND RELATED SYSTEM AND ARTICLE OF MANUFACTURE Public/Granted day:2009-01-01
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