Invention Grant
- Patent Title: Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
- Patent Title (中): 制造自对准沉积源极/漏极绝缘栅场效应晶体管的工艺
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Application No.: US11166286Application Date: 2005-06-23
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Publication No.: US07902029B2Publication Date: 2011-03-08
- Inventor: Daniel E. Grupp , Daniel J. Connelly , Paul A. Clifton , Carl M. Faulkner
- Applicant: Daniel E. Grupp , Daniel J. Connelly , Paul A. Clifton , Carl M. Faulkner
- Applicant Address: US CA Santa Monica
- Assignee: Acorn Technologies, Inc.
- Current Assignee: Acorn Technologies, Inc.
- Current Assignee Address: US CA Santa Monica
- Agency: SNR Denton US LLP
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Processes for forming self-aligned, deposited source/drain, insulated gate, transistors and, in particular, FETs. By depositing a source/drain in a recess such that it remains only in the recess, the source/drain can be formed self-aligned to a gate and/or a channel of such a device. For example, in one such process a gate structure of a transistor may be formed and, in a material surrounding the gate structure, a recess created so as to be aligned to an edge of the gate structure. Subsequently, a source/drain conducting material may be deposited in the recess. Such a source/drain conducting material may be deposited, in some cases, as layers, with one or more such layers being planarized following its deposition. In this way, the conducting material is kept within the boundaries of the recess.
Public/Granted literature
- US20060084232A1 Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor Public/Granted day:2006-04-20
Information query
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