Invention Grant
- Patent Title: Semiconductor device including vertical MOS transistors
- Patent Title (中): 半导体器件包括垂直MOS晶体管
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Application No.: US12239048Application Date: 2008-09-26
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Publication No.: US07902573B2Publication Date: 2011-03-08
- Inventor: Kiyonori Oyu
- Applicant: Kiyonori Oyu
- Applicant Address: JP Tokyo
- Assignee: Elpida Memory, Inc.
- Current Assignee: Elpida Memory, Inc.
- Current Assignee Address: JP Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2007-251130 20070927
- Main IPC: H01L23/52
- IPC: H01L23/52

Abstract:
A semiconductor device includes: a plurality of vertical MOS transistors sharing a gate electrode (2) of a first conductivity type; first semiconductor pillars (3, 4 and 5) with a gate insulating film (18) formed therearound, across the gate insulating film (18) the vertical MOS transistors facing the gate electrode; and a second semiconductor pillar (8) being of the first conductivity type which is the same as the conductivity type of the gate electrode and being in contact with the gate electrode at a portion thereof from which at least a part of the gate insulating film is removed, wherein potential supply (6) to the shared gate electrode (2) is effected through the second semiconductor pillar (8).
Public/Granted literature
- US20090085098A1 SEMICONDUCTOR DEVICE INCLUDING VERTICAL MOS TRANSISTORS Public/Granted day:2009-04-02
Information query
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