发明授权
US07907433B2 Semiconductor memory device and method of performing data reduction test
有权
半导体存储器件和执行数据压缩测试的方法
- 专利标题： Semiconductor memory device and method of performing data reduction test
- 专利标题（中）： 半导体存储器件和执行数据压缩测试的方法
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申请号： US12385949申请日： 2009-04-24
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公开(公告)号： US07907433B2公开(公告)日： 2011-03-15
- 发明人: Hideo Nomura , Tomonori Hayashi , Yuji Sugiyama
- 申请人： Hideo Nomura , Tomonori Hayashi , Yuji Sugiyama
- 申请人地址： JP Tokyo
- 专利权人： Elpida Memory, Inc.
- 当前专利权人： Elpida Memory, Inc.
- 当前专利权人地址： JP Tokyo
- 代理机构： Foley & Lardner LLP
- 优先权： JP2008-115828 20080425
- 主分类号： G11C5/02
- IPC分类号： G11C5/02
摘要：
A semiconductor device includes a plurality of package terminals included in a package, a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals, and a plurality of data line control switch disposed between the plurality of package terminals and the plurality of data input/output terminals. The plurality of data line control switches of each of the chips connects the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode. The plurality of data line control switches connects different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode. The respective groups of the data input/output terminals belong to the plurality of data input/output terminals. The respective groups of the package terminals are different between different ones of the chips.
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