Invention Grant
- Patent Title: Built-in jitter measurement circuit
- Patent Title (中): 内置抖动测量电路
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Application No.: US11870113Application Date: 2007-10-10
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Publication No.: US07912166B2Publication Date: 2011-03-22
- Inventor: Jen-Chien Hsu , Hung-Wen Lu , Chau-Chin Su , Yeong-Jar Chang
- Applicant: Jen-Chien Hsu , Hung-Wen Lu , Chau-Chin Su , Yeong-Jar Chang
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: Faraday Technology Corp.
- Current Assignee: Faraday Technology Corp.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A jitter measurement circuit and a method for calibrating the jitter measurement circuit are disclosed. The jitter measurement circuit includes a synchronous dual-phase detector and a decision circuit. In a test mode, a probability distribution function (PDF) of the jitter of a clock signal output by a circuit under test is obtained. In a calibration mode, a random clock, which is externally generated or generated by a free-run oscillator in the circuit under test, is used to calibrate the synchronous dual-phase detector. The decision circuit performs logic operations, data latching and counting on a phase relationship detected by the synchronous dual-phase detector in order to obtain a counting value and a PDF relative to the jitter of the clock signal.
Public/Granted literature
- US20090096439A1 BUILT-IN JITTER MEASUREMENT CIRCUIT Public/Granted day:2009-04-16
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