Invention Grant
- Patent Title: Method of verifying a layout pattern
- Patent Title (中): 验证布局模式的方法
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Application No.: US11752310Application Date: 2007-05-23
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Publication No.: US07913196B2Publication Date: 2011-03-22
- Inventor: Te-Hung Wu , Chia-Wei Huang , Chuen Huei Yang , Sheng-Yuan Huang , Pei-Ru Tsai , Chih-Hao Wu
- Applicant: Te-Hung Wu , Chia-Wei Huang , Chuen Huei Yang , Sheng-Yuan Huang , Pei-Ru Tsai , Chih-Hao Wu
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of verifying a layout pattern comprises separately steps of obtaining a simulated pattern at a lower portion of a film by using a layout pattern as a mask to transfer the layout pattern to the film, and obtaining a simulated pattern at an upper portion of the film by using the layout pattern as a mask to transfer the layout pattern to the film. The layout pattern is verified according to the upper and lower simulated patterns.
Public/Granted literature
- US20080295062A1 Method of verifying a layout pattern Public/Granted day:2008-11-27
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