A pixel array substrate including a substrate, a first patterned conductive layer, a second patterned conductive layer, and pixel electrodes is provided. The first patterned conductive layer has scan lines and gate electrodes. The second patterned conductive layer has data lines, source electrodes, drain electrodes, and capacitor electrodes. The data lines and the scan lines define many pixel areas. Many pixel storage capacitances CST is formed between the capacitor electrodes and the first patterned conductive layer. Many gate/drain capacitances CGD is formed in an overlapping area of the drain electrodes and gate electrodes. A liquid crystal capacitance CLC is formed above each pixel electrode. In at least one pixel area, the capacitance ratio of CST and CGD is α, the capacitance ratio of CLC and CST is β, and the ratio of a first deviation of CST and a second deviation of CGD is within the range of α(1+β)(1±50%).