Method and system for reducing critical dimension side-to-side tilting error

Invention Grant

US07917244B2 Method and system for reducing critical dimension side-to-side tilting error 有权

Title translation: 减少临界尺寸侧向倾斜误差的方法和系统

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Patent Title: Method and system for reducing critical dimension side-to-side tilting error
Patent Title (中): 减少临界尺寸侧向倾斜误差的方法和系统
Application No.: US11686238

Application Date: 2007-03-14
Publication No.: US07917244B2

Publication Date: 2011-03-29
Inventor: Cheng-Ming Lin , Chai-Wei Chang
Applicant: Cheng-Ming Lin , Chai-Wei Chang
Applicant Address: TW Hsin-Chu
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
Current Assignee Address: TW Hsin-Chu
Agency: Haynes and Boone, LLP
Main IPC: G06F19/00
IPC: G06F19/00 ; G03C5/00

Method and system for reducing critical dimension side-to-side tilting error

Abstract:

A method for reducing a critical dimension error of a substrate is provided. A first function is identified for correlating a critical dimension error with a first effect. A second function is identified for correlating a critical dimension error with a scan speed. An optimal scan speed for minimizing the critical dimension error is identified by substantially equating the first function and the second function. The substrate may be a mask or a wafer.

Abstract(Chinese):

提供了一种降低衬底临界尺寸误差的方法。识别出关键维度误差与第一效应相关联的第一功能。识别出关键尺寸误差与扫描速度相关的第二个功能。用于最小化临界尺寸误差的最佳扫描速度通过基本上等同于第一功能和第二功能来识别。衬底可以是掩模或晶片。

Public/Granted literature

US20080228309A1 Method and System for Reducing Critical Dimension Side-to-Side Tilting Error Public/Granted day:2008-09-18

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