发明授权
- 专利标题: Device for implementing a sum of products expression
- 专利标题(中): 用于实现产品表达式总和的设备
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申请号: US11254935申请日: 2005-10-20
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公开(公告)号: US07917569B2公开(公告)日: 2011-03-29
- 发明人: Aditya Bhuvanagiri , Rakesh Malik , Nitin Chawla
- 申请人: Aditya Bhuvanagiri , Rakesh Malik , Nitin Chawla
- 申请人地址: IN Noida, Uttar Pradesh
- 专利权人: STMicroelectronics Pvt. Ltd.
- 当前专利权人: STMicroelectronics Pvt. Ltd.
- 当前专利权人地址: IN Noida, Uttar Pradesh
- 代理机构: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- 代理商 Lisa K. Jorgenson
- 优先权: IN2054/DEL/2004 20041020
- 主分类号: G06F7/00
- IPC分类号: G06F7/00
摘要:
A device for implementing a sum-of-products expression includes a first set of 2-input Shift-and-Add (2SAD) blocks receiving a coefficient set/complex sum-of-products expression for generating a first set of partially optimized expression terms by applying recursive optimization therein, a second set of 1-input Shift-and-Add (1SAD) blocks receiving response from the 2SAD blocks for generating a second set of partially optimized expression terms by applying vertical optimization therein, a third set of 2SAD blocks receiving recursively and vertically optimized response from the first set of 2SAD block and the second set of 1SAD blocks for generating a third set of partially optimized expression terms by applying horizontal optimization therein, a fourth set of 2SAD blocks receiving response from the blocks for generating a fourth set of partially optimized expression terms by applying decomposition and factorization, and a fifth set of 2SAD blocks receiving response from the fourth set of 2SAD blocks, for generating the final output.
公开/授权文献
- US20060153321A1 Device for implementing a sum of products expression 公开/授权日:2006-07-13