发明授权
US07919388B2 Methods for fabricating semiconductor devices having reduced gate-drain capacitance
有权
制造具有降低的栅 - 漏电容的半导体器件的方法
- 专利标题： Methods for fabricating semiconductor devices having reduced gate-drain capacitance
- 专利标题（中）： 制造具有降低的栅 - 漏电容的半导体器件的方法
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申请号： US12627739申请日： 2009-11-30
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公开(公告)号： US07919388B2公开(公告)日： 2011-04-05
- 发明人: Ljubo Radic , Edouard D. de Frésart
- 申请人： Ljubo Radic , Edouard D. de Frésart
- 申请人地址： US TX Austin
- 专利权人： Freescale Semiconductor, Inc.
- 当前专利权人： Freescale Semiconductor, Inc.
- 当前专利权人地址： US TX Austin
- 代理机构： Ingrassia Fisher & Lorenz, P.C.
- 主分类号： H01L29/72
- IPC分类号： H01L29/72
摘要：
Embodiments of a method for fabricating a semiconductor device having a reduced gate-drain capacitance are provided. In one embodiment, the method includes the steps of etching a trench in a semiconductor substrate utilizing an etch mask, widening the trench to define overhanging regions of the etch mask extending partially over the trench, and depositing a gate electrode material into the trench and onto the overhanging regions. The gate electrode material merges between the overhanging regions prior to the filling of the trench to create an empty fissure within the trench. A portion of the semiconductor substrate is removed through the empty fissure to form a void cavity proximate the trench.
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