- 专利标题： Structure of high performance combo chip and processing method
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申请号： US12269064申请日： 2008-11-12
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公开(公告)号： US07919873B2公开(公告)日： 2011-04-05
- 发明人: Jin-Yuan Lee , Mou-Shiung Lin
- 申请人： Jin-Yuan Lee , Mou-Shiung Lin
- 申请人地址： TW Hsinchu
- 专利权人： Megica Corporation
- 当前专利权人： Megica Corporation
- 当前专利权人地址： TW Hsinchu
- 代理机构： McDermott Will & Emery LLP
- 主分类号： H01L29/40
- IPC分类号： H01L29/40
摘要：
A method for fabricating a chip package is achieved. A seed layer is formed over a silicon wafer. A photoresist layer is formed on the seed layer, an opening in the photoresist layer exposing the seed layer. A first solder bump is formed on the seed layer exposed by the opening. The photoresist layer is removed. The seed layer not under the first solder bump is removed. A second solder bump on a chip is joined to the first solder bump.
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