Dual gate structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method

Invention Grant

US07939401B2 Dual gate structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method 有权

Title translation: 双栅极结构，其制造方法，具有该栅极结构的半导体器件和半导体器件制造方法

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Patent Title: Dual gate structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method
Patent Title (中): 双栅极结构，其制造方法，具有该栅极结构的半导体器件和半导体器件制造方法
Application No.: US12618044

Application Date: 2009-11-13
Publication No.: US07939401B2

Publication Date: 2011-05-10
Inventor: Heesook Park , Jaehwa Park , Janghee Lee , Geumjung Seong , Byunghak Lee , Dongchan Lim , Taeho Cha
Applicant: Heesook Park , Jaehwa Park , Janghee Lee , Geumjung Seong , Byunghak Lee , Dongchan Lim , Taeho Cha
Applicant Address: KR Suwon-Si
Assignee: Samsung Electronics Co., Ltd.
Current Assignee: Samsung Electronics Co., Ltd.
Current Assignee Address: KR Suwon-Si
Agency: F. Chau & Associates, LLC
Priority: KR2005-73415 20050810
Main IPC: H01L21/8238
IPC: H01L21/8238

Dual gate structure, fabrication method for the same, semiconductor device having the same, and semiconductor device fabrication method

Abstract:

In one embodiment, a semiconductor device includes at least two stacked gate structures formed on a substrate. The two stacked gate structures each include a semiconductor layer and a metal layer over the semiconductor layer. The two stacked gate structures on the substrate are characterized by differential intermediate layers, one of the two structures including an ohmic layer and the other of the two structures not including an ohmic layer.

Abstract(Chinese):

在一个实施例中，半导体器件包括形成在衬底上的至少两个堆叠栅极结构。两个堆叠的栅极结构各自包括在半导体层上的半导体层和金属层。衬底上的两个堆叠的栅极结构的特征在于差分中间层，两个结构中的一个结构包括欧姆层，并且两个结构中的另一个不包括欧姆层。

Public/Granted literature

US20100055891A1 DUAL GATE STRUCTURE, FABRICATION METHOD FOR THE SAME, SEMICONDUCTOR DEVICE HAVING THE SAME, AND SEMICONDUCTOR DEVICE FABRICATION METHOD Public/Granted day:2010-03-04

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS