Invention Grant
- Patent Title: Fractional delay-locked loops
- Patent Title (中): 小数延迟锁定环
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Application No.: US12701346Application Date: 2010-02-05
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Publication No.: US07940098B1Publication Date: 2011-05-10
- Inventor: Tad Kwasniewski , Farhad Zarkeshvari
- Applicant: Tad Kwasniewski , Farhad Zarkeshvari
- Applicant Address: US CA San Jose
- Assignee: Altera Corporation
- Current Assignee: Altera Corporation
- Current Assignee Address: US CA San Jose
- Agent Steven J. Cahill
- Main IPC: H03K7/06
- IPC: H03K7/06

Abstract:
A phase-locked loop includes a phase-to-digital converter that receives a first periodic input signal at a first input and a first feedback signal at a second input. The phase-to-digital converter generates digital signals. A digitally controlled oscillator includes a delay-locked loop that is responsive to the digital signals. The delay-locked loop generates a periodic output signal having an average frequency that is a product of a frequency of the first periodic input signal multiplied by a non-integer fractional number while a phase of the first periodic input signal is unchanging.
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