A clock generator includes a delta sigma modulator, a counter and a first phase lock loop. The delta sigma modulator sequentially generates a plurality of variable parameters according to a predetermined value and a first input clock signal. The counter, which is connected to the delta sigma modulator, is used to generate an output clock signal in accordance with a counting value and a second input clock signal. The counting value is relevant to the variable parameters. The first phase lock loop, which is connected to the output of the counter, is used to generate an objective clock signal in accordance with the output clock signal.