发明授权
US07947533B2 Void free soldering semiconductor chip attachment method for wafer scale chip size 有权
半自由焊接半导体芯片贴片方法用于晶片尺寸芯片尺寸

  • 专利标题: Void free soldering semiconductor chip attachment method for wafer scale chip size
  • 专利标题(中): 半自由焊接半导体芯片贴片方法用于晶片尺寸芯片尺寸
  • 申请号: US11865310
    申请日: 2007-10-01
  • 公开(公告)号: US07947533B2
    公开(公告)日: 2011-05-24
  • 发明人: Narase Soodprasert
  • 申请人: Narase Soodprasert
  • 代理商 Narase Soodprasert
  • 主分类号: H01L21/00
  • IPC分类号: H01L21/00
Void free soldering semiconductor chip attachment method for wafer scale chip size
摘要:
Methods for attaching the wafer scale semiconductor chip, up to 4 square inch (2.times.2 inchs), are comprises of following steps. Stack assembles following materials from bottom to top. First lower integrated heat spreader (IHS). Second thermal interface material (TIM). Third semiconductor chip with backside metallization deposit. Forth polyimide film. Fifth the dummy upper IHS. Then put the stack-assembled set into the metal box and fix in place. Then the metal box and stack-assembled set in it are heated to wetting temperature of TIM. During cool down, the environment temperature must be set at a few degrees lower than the melting point of TIM, to soak the stack-assembled set at melting point of TIM until the TIM completely become solid, then cool down to room temperature. After de-assemble and remove upper IHS and polyimide film, we will get the void free soldering of semiconductor chip on lower IHS.
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