Invention Grant
- Patent Title: Chip stack package and method of fabricating the same
- Patent Title (中): 芯片堆叠封装及其制造方法
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Application No.: US12100359Application Date: 2008-04-09
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Publication No.: US07948089B2Publication Date: 2011-05-24
- Inventor: Hyun-Soo Chung , Dong-Ho Lee , Nam-Seog Kim , Son-Kwan Hwang
- Applicant: Hyun-Soo Chung , Dong-Ho Lee , Nam-Seog Kim , Son-Kwan Hwang
- Applicant Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Priority: KR10-2007-0035176 20070410
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A chip stack package is provided, wherein semiconductor chips having different die sizes are stacked by arranging pads in a scribe region through a redistribution process, so that the thickness of the package can be reduced. A method of fabricating the chip stack package is also provided. In the chip stack package, a plurality of circuit patterns are arranged on one surface of a substrate, and a unit semiconductor chip is mounted thereon. The unit semiconductor chip includes a plurality of semiconductor chips sequentially stacked on the substrate. The semiconductor chips of the unit semiconductor chip have different die sizes. One of the semiconductor chips includes a plurality of first pads arranged in a first chip region, and the other semiconductor chips include second pads arranged in a scribe region at an outside of a second chip region defined by the scribe region.
Public/Granted literature
- US20080251939A1 CHIP STACK PACKAGE AND METHOD OF FABRICATING THE SAME Public/Granted day:2008-10-16
Information query
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