Invention Grant
- Patent Title: Semiconductor integrated circuit device and countermeasure method against NBTI degradation
- Patent Title (中): 半导体集成电路器件及对策NBTI退化对策
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Application No.: US12427202Application Date: 2009-04-21
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Publication No.: US07948261B2Publication Date: 2011-05-24
- Inventor: Shinya Kawakami
- Applicant: Shinya Kawakami
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Turocy & Watson, LLP
- Priority: JP2008-150861 20080609
- Main IPC: H03K19/003
- IPC: H03K19/003

Abstract:
A semiconductor integrated circuit device includes a target circuit of a low power consumption mode having at least one flip-flop circuit to which a clock signal is supplied in a normal operation mode and in a low power consumption mode, and a logic circuit to which each output of the at least one flip-flop circuit is input, wherein each of the flip-flop circuits includes a selector that selects a normal data signal in the normal operation mode, selects an inverted output of the flip-flop circuit in the low power consumption mode, based on an operation-mode switching signal that designates switching between the normal operation mode and the low power consumption mode, and inputs the selected signal to a data input terminal of the flip-flop circuit.
Public/Granted literature
- US20090302884A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND COUNTERMEASURE METHOD AGAINST NBTI DEGRADATION Public/Granted day:2009-12-10
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