A specialized processing block for a configurable integrated circuit device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry reuses an adder that is also available, in other configurations, for accumulation of the result. Rounding is performed by adding a constant to the result and then truncating at the bit position at which rounding is desired. The constant may be entered by a user, or may be derived based on a desired rounding method from mask data entered by the user to identify the rounding bit position.