A logic circuit computes various modal interval (MI) arithmetic values using a plurality of arithmetic function units (AFUs), each dedicated to compute a specific MI arithmetic operation. The AFUs receive first and second MI operand values each encoded in first and second operand signals. Each AFU provides a MI result value encoded in a result signal to a multiplexer. The multiplexer receives a selector signal specifying the MI arithmetic operation desired, and provides to a result register, an output signal encoding the MI result value specified by the selector signal. The result register stores the MI result value.