Invention Grant
- Patent Title: Level shifter having low duty cycle distortion
- Patent Title (中): 电平移位器具有低占空比失真
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Application No.: US11768300Application Date: 2007-06-26
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Publication No.: US07956642B2Publication Date: 2011-06-07
- Inventor: ChulKyu Lee
- Applicant: ChulKyu Lee
- Applicant Address: US CA San Diego
- Assignee: Qualcomm Incorporated
- Current Assignee: Qualcomm Incorporated
- Current Assignee Address: US CA San Diego
- Agent Howard H. Seo
- Main IPC: H03K19/094
- IPC: H03K19/094 ; H03L5/00

Abstract:
A level shifter includes an inverting circuit, a cross-coupled level shifting latch, and a SR logic gate latch. The first and second outputs of the level shifting latch are coupled to the set (S) and reset (R) inputs of the SR latch. The inverting circuit, that is powered by a first supply voltage VDDL, supplies a noninverted version of an input signal onto a first input of the level shifting latch and supplies an inverted version of the input signal onto a second input of the level shifting latch. A low-to-high transition of the input signal resets the SR latch, whereas a high-to-low transition sets the SR latch. Duty cycle distortion skew of the level shifter is less than fifty picoseconds over voltage, process and temperature corners, and the level shifter has a supply voltage margin of more than one quarter of a nominal value of VDDL.
Public/Granted literature
- US20090002027A1 LEVEL SHIFTER HAVING LOW DUTY CYCLE DISTORTION Public/Granted day:2009-01-01
Information query
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