Invention Grant
US07960244B2 Process for the aligned manufacture of electronic semiconductor devices in a SOI substrate
有权
用于在SOI衬底中对准制造电子半导体器件的工艺
- Patent Title: Process for the aligned manufacture of electronic semiconductor devices in a SOI substrate
- Patent Title (中): 用于在SOI衬底中对准制造电子半导体器件的工艺
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Application No.: US11339815Application Date: 2006-01-24
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Publication No.: US07960244B2Publication Date: 2011-06-14
- Inventor: Salvatore Leonardi , Roberto Modica
- Applicant: Salvatore Leonardi , Roberto Modica
- Applicant Address: IT Agrate Brianza
- Assignee: STMicroelectronics, S.r.l.
- Current Assignee: STMicroelectronics, S.r.l.
- Current Assignee Address: IT Agrate Brianza
- Agency: Graybeal Jackson LLP
- Agent Lisa K. Jorgenson; Kevin D. Jablonski
- Priority: EP05425096 20050224
- Main IPC: H01L21/76
- IPC: H01L21/76
Abstract:
A process for manufacturing an electronic semiconductor device, wherein a SOI wafer is provided, formed by a bottom layer of semiconductor material, an insulating layer, and a top layer of semiconductor material, stacked on top of one another; alignment marks are formed in the top layer; an implanted buried region is formed, aligned to the alignment marks; a hard mask is formed on top of the top layer so as to align it to the alignment marks; using the hard mask, the top layer is selectively removed so as to form a trench extending up to the insulating layer; there a lateral-insulation region in the trench, that is contiguous to the insulating layer and delimits with the latter an insulated well of semiconductor material; and electronic components are formed in the top layer.
Public/Granted literature
- US20060194408A1 Process and circuit for manufacturing electronic semiconductor devices in a SOI substrate Public/Granted day:2006-08-31
Information query
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