Invention Grant
US07960840B2 Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level
有权
双晶片载体工艺，用于创建具有通过硅通孔和微电子机械系统的集成电路裸片，该芯片由在晶片级产生的密封腔保护
- Patent Title: Double wafer carrier process for creating integrated circuit die with through-silicon vias and micro-electro-mechanical systems protected by a hermetic cavity created at the wafer level
- Patent Title (中): 双晶片载体工艺，用于创建具有通过硅通孔和微电子机械系统的集成电路裸片，该芯片由在晶片级产生的密封腔保护
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Application No.: US12463830Application Date: 2009-05-11
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Publication No.: US07960840B2Publication Date: 2011-06-14
- Inventor: Thomas Dyer Bonifield , Thomas W. Winter , William R. Morrison , Gregory D. Winterton , Asad M. Haider
- Applicant: Thomas Dyer Bonifield , Thomas W. Winter , William R. Morrison , Gregory D. Winterton , Asad M. Haider
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Yingsheng Tung; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L23/52
- IPC: H01L23/52
Abstract:
A TSV-MEMS packaging process is provided. The process includes forming TSVs in the front side of the product wafer, and attaching a first carrier to the front side of the product wafer, subsequent to forming TSVs. The process further includes thinning the back side of the product wafer to expose TSV tips, detaching the first carrier from the front side of the product wafer, and transferring the thinned wafer to a second carrier with back side adhered to the second wafer carrier. Semiconductor components are added to the front side of the product wafer, followed by forming a hermetic cavity over the added semiconductor components, and detaching the second carrier from the back side of the product wafer. Wafer level processing continues after detaching the second carrier.
Public/Granted literature
Information query
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