发明授权
US07961018B2 Semiconductor device including delay locked loop having periodically activated replica path
有权
半导体器件包括具有周期性激活的复制路径的延迟锁定环
- 专利标题: Semiconductor device including delay locked loop having periodically activated replica path
- 专利标题(中): 半导体器件包括具有周期性激活的复制路径的延迟锁定环
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申请号: US12588571申请日: 2009-10-20
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公开(公告)号: US07961018B2公开(公告)日: 2011-06-14
- 发明人: Seok-Hun Hyun , Kye-Hyun Kyung , Jun-Ho Shin
- 申请人: Seok-Hun Hyun , Kye-Hyun Kyung , Jun-Ho Shin
- 申请人地址: KR Suwon-si, Gyeonggi-do
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人地址: KR Suwon-si, Gyeonggi-do
- 代理机构: Lee & Morse, P.C.
- 优先权: KR10-2008-0103834 20081022
- 主分类号: H03L7/06
- IPC分类号: H03L7/06
摘要:
A delay locked loop adapted to delay an external clock signal and to output an internal clock signal, the delay locked loop including a renewal signal generator that outputs a renewal signal that is selectively activated and inactivated, a replica path that is active when the renewal signal is activated and is inactive when the renewal signal is inactivated, the replica path delaying the internal clock signal by a delay time of a normal path of a semiconductor device to output a replica internal clock signal when the renewal signal is activated, a control signal generator adapted to vary and to output a delay control signal according to a phase difference between the external and the replica internal clock signals, and a variable delay circuit adapted to delay the external clock signal by a time corresponding to the delay control signal and to output the internal clock signal.