发明授权
US07964942B2 Lead frame having a die stage smaller than a semiconductor device and a semiconductor device using the same 有权
具有小于半导体器件的裸片级的引线框和使用其的半导体器件

  • 专利标题: Lead frame having a die stage smaller than a semiconductor device and a semiconductor device using the same
  • 专利标题(中): 具有小于半导体器件的裸片级的引线框和使用其的半导体器件
  • 申请号: US11938742
    申请日: 2007-11-12
  • 公开(公告)号: US07964942B2
    公开(公告)日: 2011-06-21
  • 发明人: Kenichi ShirasakaHirotaka Eguchi
  • 申请人: Kenichi ShirasakaHirotaka Eguchi
  • 申请人地址: JP Shizuoka-ken
  • 专利权人: Yamaha Corporation
  • 当前专利权人: Yamaha Corporation
  • 当前专利权人地址: JP Shizuoka-ken
  • 代理机构: Dickstein Shapiro LLP
  • 优先权: JP2003-151378 20030528; JP2004-133376 20040428
  • 主分类号: H01L23/495
  • IPC分类号: H01L23/495
Lead frame having a die stage smaller than a semiconductor device and a semiconductor device using the same
摘要:
A lead frame has a die stage for mounting a semiconductor chip whose electrodes are electrically connected with leads via bonding wires, wherein they are enclosed in a molded resin, thus producing a semiconductor device. The outline of the die stage is shaped so as to be smaller than the outline of the semiconductor chip, and a plurality of cutouts are formed in the peripheral portion of the die stage so as to reduce the overall area of the die stage and to enhance the adhesion between the die stage and molded resin. The length L2 of each cutout ranges from (L1×0.05) to (L1×0.20) where L1 denotes the length of each side of the die stage, and the overall area S2 of the die stage ranges from (S1×0.10) to (S1×0.40) where S1 denotes the overall area of the semiconductor chip.
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