Invention Grant
- Patent Title: Transmitting apparatus with bit arrangement method
- Patent Title (中): 带排列方式的发送装置
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Application No.: US12836860Application Date: 2010-07-15
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Publication No.: US07965791B2Publication Date: 2011-06-21
- Inventor: Tetsuya Yano , Kazuhisa Obuchi , Shunji Miyazaki
- Applicant: Tetsuya Yano , Kazuhisa Obuchi , Shunji Miyazaki
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Myers Wolin, LLC.
- Priority: JP2004-035768 20040212
- Main IPC: H04L27/36
- IPC: H04L27/36

Abstract:
A method of transmitting data including controlling generation of bit sequences to adjust an occupation rate occupied with predetermined bits included in a first data block, which is obtained by encoding first data, to be closer to an occupation rate occupied with predetermined bits included in a second data block, which is obtained by encoding second data. With regard to first bit positions of the predetermined bits, the first bit positions being distinguished from second bit positions based on an error tolerance resulting from a correspondence to a signal point on a phase plane. Wherein a sum of a number of the predetermined bits included in the first data block and the predetermined bits included in the second data block is less than a total number of the first bit positions. Also including performing multi-level modulation for transmission based on the generated bit sequences.
Public/Granted literature
- US20100278282A1 TRANSMITTING APPARATUS WITH BIT ARRANGEMENT METHOD Public/Granted day:2010-11-04
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