发明授权
- 专利标题： Semiconductor device reducing output capacitance due to parasitic capacitance
- 专利标题（中）： 半导体器件由于寄生电容而降低输出电容
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申请号： US12474700申请日： 2009-05-29
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公开(公告)号： US07968943B2公开(公告)日： 2011-06-28
- 发明人: Takuya Sunada , Kazuhiko Kusuda , Takeshi Yoshida
- 申请人： Takuya Sunada , Kazuhiko Kusuda , Takeshi Yoshida
- 申请人地址： JP Osaka
- 专利权人： Panasonic Electric Works Co., Ltd.
- 当前专利权人： Panasonic Electric Works Co., Ltd.
- 当前专利权人地址： JP Osaka
- 代理机构： Greenblum & Bernstein, P.L.C.
- 优先权： JP2008-165591 20080625
- 主分类号： H01L29/76
- IPC分类号： H01L29/76
摘要：
Plural through-holes are formed in a region of a semiconductor substrate positioned below a drain region (an element region other than a P-type well region). According to this configuration, an opposing area of the drain region and the semiconductor substrate can be reduced. Therefore, a drain-substrate capacitance Cdsub is reduced, and an output capacitance Coss of an SOI LDMOSFET can be reduced as a result.
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