An embedded chip package includes a substrate, a semiconductor structure, an encapsulating material layer and a plurality of conductive vias. Herein the substrate includes at least a dielectric layer and at least a patterned circuit layer disposed on the dielectric layer. The semiconductor structure is disposed on the substrate and has a plurality of electrical bonding pads, and the electrical bonding pads contact the dielectric layer. The encapsulating material layer is disposed on the substrate and around the semiconductor structure. In addition, a plurality of conductive vias is disposed in the substrate to electrically connect the patterned circuit layer to the electrical bonding pads.