Invention Grant
- Patent Title: Wafer-level flip-chip assembly methods
- Patent Title (中): 晶圆级倒装芯片组装方法
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Application No.: US11800386Application Date: 2007-05-04
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Publication No.: US07977155B2Publication Date: 2011-07-12
- Inventor: Chien-Hsiun Lee , Clinton Chao , Ming-Chung Sung , Tjandra Winata Karta
- Applicant: Chien-Hsiun Lee , Clinton Chao , Ming-Chung Sung , Tjandra Winata Karta
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/66
Abstract:
A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors.
Public/Granted literature
- US20080274589A1 Wafer-level flip-chip assembly methods Public/Granted day:2008-11-06
Information query
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