Invention Grant
US07978539B2 Semiconductor device having resistance based memory array, method of reading, and systems associated therewith
有权
具有基于电阻的存储器阵列,读取方法和与其相关联的系统的半导体器件
- Patent Title: Semiconductor device having resistance based memory array, method of reading, and systems associated therewith
- Patent Title (中): 具有基于电阻的存储器阵列,读取方法和与其相关联的系统的半导体器件
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Application No.: US12292891Application Date: 2008-11-28
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Publication No.: US07978539B2Publication Date: 2011-07-12
- Inventor: Kwang Jin Lee , Byung Gil Choi
- Applicant: Kwang Jin Lee , Byung Gil Choi
- Applicant Address: KR Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Gyeonggi-do
- Agency: Harness, Dickey & Pierce
- Priority: KR10-2008-0026390 20080321
- Main IPC: G11C7/22
- IPC: G11C7/22

Abstract:
In one embodiment, the semiconductor device includes a non-volatile memory cell array. Memory cells of the non-volatile memory cell array are resistance based, and each memory cell has a resistance that changes over time after data is written into the memory cell. A write address buffer is configured to store write addresses associated with data being written into the non-volatile memory cell array, and a read unit is configured to perform a read operation to read data from the non-volatile memory cell array. The read unit is configured to control a read current applied to the non-volatile memory cell array during the read operation based on whether a read address matches one of the stored write addresses and at least one indication of settling time of the data being written into the non-volatile memory cell array.
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