发明授权
- 专利标题: Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same
- 专利标题(中): 用于集成电路物理设计过程中使用的冗余微环结构的设计结构及其形成方法
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申请号: US11955580申请日: 2007-12-13
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公开(公告)号: US07984394B2公开(公告)日: 2011-07-19
- 发明人: Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
- 申请人: Brent A. Anderson , Jeanne P. Bickford , Markus Buehler , Jason D. Hibbeler , Juergen Koehl , Edward J. Nowak
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Downs Rachlin Martin PLLC
- 主分类号: G06F17/50
- IPC分类号: G06F17/50
摘要:
A design structure for an integrated circuit including a first wire of a first level of wiring tracks, a second wire of a second level of wiring tracks, a third wire of a third level of wiring tracks, and a fourth wire located a first distance from the second wire in the second level of wiring tracks. A first via connects the first and second wires at a first location of the second wire. A second via connects the second and third wires at the first location, the second via is substantially axially aligned with the first via. A third via connecting the third and fourth wires at a second location of the fourth wire. A fourth via connecting the first and fourth wires at the second location, the fourth via is substantially axially aligned with the third via. The second, third, and fourth vias, and the third and fourth wires form a path between the first and second wires redundant to the first via.
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