Invention Grant
- Patent Title: Self-biased phase locked loop
- Patent Title (中): 自偏置锁相环
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Application No.: US12464687Application Date: 2009-05-12
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Publication No.: US07986191B2Publication Date: 2011-07-26
- Inventor: Jinzhong Peng , Zhigang Chiachi Fu
- Applicant: Jinzhong Peng , Zhigang Chiachi Fu
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Squire, Sanders & Dempsey (US) LLP
- Priority: CN200810038210 20080526
- Main IPC: H03L7/00
- IPC: H03L7/00

Abstract:
A self-biased PLL includes a first charge pump and a second charge pump, an output terminal of the first charge pump is connected with a discharge-charge capacitor to output a control voltage, an output terminal of the second charge pump is connected with an output terminal of a bias generator for outputting a first bias voltage equal to the control voltage, wherein, a current output from the first charge pump is equal to a value obtained through dividing the production of a first constant with a bias current of a voltage control oscillator by a frequency division factor of a frequency divider; a current output from the second charge pump is equal to a value obtained through dividing the bias current of the voltage control oscillator by a second constant; and a multiple relation exists between an output resistance of the bias generator and an equivalent resistance of a differential buffer delay stage in the voltage control oscillator.
Public/Granted literature
- US20090289726A1 Self-Biased Phase Locked Loop Public/Granted day:2009-11-26
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