发明授权
- 专利标题: Self-biased phase locked loop
- 专利标题(中): 自偏置锁相环
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申请号: US12464687申请日: 2009-05-12
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公开(公告)号: US07986191B2公开(公告)日: 2011-07-26
- 发明人: Jinzhong Peng , Zhigang Chiachi Fu
- 申请人: Jinzhong Peng , Zhigang Chiachi Fu
- 申请人地址: CN Shanghai
- 专利权人: Semiconductor Manufacturing International (Shanghai) Corporation
- 当前专利权人: Semiconductor Manufacturing International (Shanghai) Corporation
- 当前专利权人地址: CN Shanghai
- 代理机构: Squire, Sanders & Dempsey (US) LLP
- 优先权: CN200810038210 20080526
- 主分类号: H03L7/00
- IPC分类号: H03L7/00
摘要:
A self-biased PLL includes a first charge pump and a second charge pump, an output terminal of the first charge pump is connected with a discharge-charge capacitor to output a control voltage, an output terminal of the second charge pump is connected with an output terminal of a bias generator for outputting a first bias voltage equal to the control voltage, wherein, a current output from the first charge pump is equal to a value obtained through dividing the production of a first constant with a bias current of a voltage control oscillator by a frequency division factor of a frequency divider; a current output from the second charge pump is equal to a value obtained through dividing the bias current of the voltage control oscillator by a second constant; and a multiple relation exists between an output resistance of the bias generator and an equivalent resistance of a differential buffer delay stage in the voltage control oscillator.
公开/授权文献
- US20090289726A1 Self-Biased Phase Locked Loop 公开/授权日:2009-11-26
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