发明授权
US07992041B2 Peripheral device, integrated circuit for peripheral device and method for analyzing failure of peripheral device 有权
外围设备,外围设备集成电路及外围设备故障分析方法

  • 专利标题: Peripheral device, integrated circuit for peripheral device and method for analyzing failure of peripheral device
  • 专利标题(中): 外围设备,外围设备集成电路及外围设备故障分析方法
  • 申请号: US12376257
    申请日: 2007-08-03
  • 公开(公告)号: US07992041B2
    公开(公告)日: 2011-08-02
  • 发明人: Kazushi Yamamoto
  • 申请人: Kazushi Yamamoto
  • 申请人地址: JP Osaka
  • 专利权人: Panasonic Corporation
  • 当前专利权人: Panasonic Corporation
  • 当前专利权人地址: JP Osaka
  • 代理机构: Wenderoth, Lind & Ponack, L.L.P.
  • 优先权: JP2006-212487 20060803
  • 国际申请: PCT/JP2007/065245 WO 20070803
  • 国际公布: WO2008/016136 WO 20080207
  • 主分类号: G06F11/00
  • IPC分类号: G06F11/00
Peripheral device, integrated circuit for peripheral device and method for analyzing failure of peripheral device
摘要:
The peripheral device through an interface cable, and includes a second memory device for storing an evaluation program for evaluating the peripheral device and its integrated circuit. A detection section detects whether the mode indicating signal which is transmitted from the computer indicates a test mode or a normal mode, and a starting means starts the evaluation program on the second memory device when the detection section detects that the mode indicates signal a test mode.
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