发明授权
- 专利标题： Semiconductor device with offset stacked integrated circuits
- 专利标题（中）： 具有偏移堆叠集成电路的半导体器件
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申请号： US12167228申请日： 2008-07-02
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公开(公告)号： US07994623B2公开(公告)日： 2011-08-09
- 发明人: Itaru Nonomura , Kenichi Osada , Makoto Saen
- 申请人： Itaru Nonomura , Kenichi Osada , Makoto Saen
- 申请人地址： JP Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JP Tokyo
- 代理机构： Miles & Stockbridge P.C.
- 优先权： JP2007-185425 20070717
- 主分类号： H01L23/02
- IPC分类号： H01L23/02 ; H01L27/00
摘要：
A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.
公开/授权文献
- US20090021974A1 SEMICONDUCTOR DEVICE 公开/授权日：2009-01-22
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