Invention Grant
US08006072B2 Reducing data hazards in pipelined processors to provide high processor utilization 有权
降低流水线处理器中的数据危害,提供高处理器利用率

Reducing data hazards in pipelined processors to provide high processor utilization
Abstract:
A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data.
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