发明授权
US08006244B2 Controller for multiple instruction thread processors 失效
多指令线程处理器的控制器

Controller for multiple instruction thread processors
摘要:
A mechanism controls a multi-thread processor so that when a first thread encounters a latency event for a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
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