发明授权
- 专利标题： Four-gate transistor analog multiplier circuit
- 专利标题（中）： 四门晶体管模拟乘法电路
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申请号： US11804893申请日： 2007-05-21
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公开(公告)号： US08010591B2公开(公告)日： 2011-08-30
- 发明人: Mohammad M. Mojarradi , Benjamin Blalock , Sorin Cristoloveanu , Suheng Chen , Kerem Akarvardar
- 申请人： Mohammad M. Mojarradi , Benjamin Blalock , Sorin Cristoloveanu , Suheng Chen , Kerem Akarvardar
- 申请人地址： US CA Pasadena
- 专利权人： California Institute of Technology
- 当前专利权人： California Institute of Technology
- 当前专利权人地址： US CA Pasadena
- 代理机构： Milstein Zhang & Wu LLC
- 代理商 Joseph B. Milstein
- 主分类号： G06E3/00
- IPC分类号： G06E3/00
摘要：
A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.
公开/授权文献
- US20080001658A1 Four-gate transistor analog multiplier circuit 公开/授权日：2008-01-03
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