发明授权
- 专利标题: Wafer level chip scale package system
- 专利标题(中): 晶圆级芯片级封装系统
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申请号: US11618647申请日: 2006-12-29
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公开(公告)号: US08012867B2公开(公告)日: 2011-09-06
- 发明人: Koo Hong Lee , Il Kwon Shim , Young Cheol Kim , Bongsuk Choi
- 申请人: Koo Hong Lee , Il Kwon Shim , Young Cheol Kim , Bongsuk Choi
- 申请人地址: SG Singapore
- 专利权人: Stats Chippac Ltd
- 当前专利权人: Stats Chippac Ltd
- 当前专利权人地址: SG Singapore
- 代理商 Mikio Ishimaru
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
A wafer level chip scale package system is provided including placing a first integrated circuit over a semiconductor wafer having a second integrated circuit; connecting a second electrical interconnect between the first integrated circuit and the second integrated circuit; forming a stress relieving encapsulant on the outer perimeter of the second integrated circuit for covering the second electrical interconnect; and singulating a chip scale package, from the semiconductor wafer, through the stress relieving encapsulant and the semiconductor wafer.
公开/授权文献
- US20070178667A1 WAFER LEVEL CHIP SCALE PACKAGE SYSTEM 公开/授权日:2007-08-02