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发明授权
US08014477B1 Receiver employing selectable A/D sample clock frequency 有权
接收机采用可选择的A / D采样时钟频率

Receiver employing selectable A/D sample clock frequency
摘要：
A receiver is set forth that includes a tuner circuit and a converter circuit. The tuner circuit provides an analog signal corresponding to a modulated signal that is received on a selected channel. The converter circuit includes a sample clock that is used to convert the analog signal to a digital signal at a conversion rate corresponding to the frequency of the sample clock. The sample clock is selectable between at least two different clock frequencies.
摘要（中）：

提出了包括调谐器电路和转换器电路的接收器。 调谐器电路提供对应于在所选频道上接收的调制信号的模拟信号。 转换器电路包括采样时钟，该采样时钟用于以与采样时钟的频率对应的转换速率将模拟信号转换为数字信号。 采样时钟可在至少两个不同的时钟频率之间选择。

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