A circuit arrangement is provided comprising a first partial circuit to receive a supply voltage, a second partial circuit to receive an output signal of the first partial circuit and a first clock signal, the second partial circuit to store the output signal of the first partial circuit depending on the first clock signal, and a control unit to decouple the supply voltage from the first partial circuit for a time period that is shorter than a cycle duration of the first clock signal, wherein the control unit is configured to receive a second clock signal which is derived from the first clock signal by delaying.