发明授权
- 专利标题: Imager, imaging circuit, and image processing circuit
- 专利标题(中): 成像仪,成像电路和图像处理电路
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申请号: US12303379申请日: 2008-02-19
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公开(公告)号: US08023002B2公开(公告)日: 2011-09-20
- 发明人: Masaya Kinoshita , Takashi Kameya
- 申请人: Masaya Kinoshita , Takashi Kameya
- 申请人地址: JP Tokyo
- 专利权人: Sony Corporation
- 当前专利权人: Sony Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- 优先权: JP2007-124136 20070509
- 国际申请: PCT/JP2008/052724 WO 20080219
- 国际公布: WO2008/139761 WO 20081120
- 主分类号: H04N5/235
- IPC分类号: H04N5/235 ; H04N5/232 ; H04N7/01 ; H04N5/16 ; H04L12/50 ; H04L7/212 ; H04L12/28 ; G06F13/12
摘要:
The number of channels is changed in accordance with an operation mode in an image pickup apparatus. An image-pickup control unit 240 determines the number of operation channels W in accordance with an operation mode. A sensor unit 210 outputs an image pickup signal corresponding to each pixel in accordance with the number of operation channels W. A data sending unit 220 performs serial conversion on image pickup signals, and transfers them to the image processing unit 300 using a high-speed interface (a signal line 229) such as an LVDS in accordance with the number of operation channels W. A data receiving unit 311 performs parallel conversion on the transferred serial signal for each of the channels in units of M bits. A data reconstruction unit 500 detects a synchronization code embedded in the parallel signals, extracts data windows, and supplies, to a signal line 319, image pickup signals of bit length n which are reconstructed from the data windows. A clock gating circuit 330 supplies a clock CLK3 to a signal line 337 only during a period in which a valid flag (a signal line 316) indicates validity.
公开/授权文献
- US20090244303A1 IMAGER, IMAGING CIRCUIT, AND IMAGE PROCESSING CIRCUIT 公开/授权日:2009-10-01
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