Invention Grant
US08023565B2 Picture processing apparatus, semiconductor integrated circuit, and method for controlling a picture memory
失效
图像处理装置,半导体集成电路以及图像存储器的控制方法
- Patent Title: Picture processing apparatus, semiconductor integrated circuit, and method for controlling a picture memory
- Patent Title (中): 图像处理装置,半导体集成电路以及图像存储器的控制方法
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Application No.: US11475172Application Date: 2006-06-27
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Publication No.: US08023565B2Publication Date: 2011-09-20
- Inventor: Tatsuhiro Suzumura , Akihiro Oue , Kunihiko Yahagi , Shuji Michinaka , Satoshi Takekawa , Kiwamu Watanabe
- Applicant: Tatsuhiro Suzumura , Akihiro Oue , Kunihiko Yahagi , Shuji Michinaka , Satoshi Takekawa , Kiwamu Watanabe
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2005-186993 20050627
- Main IPC: H04N7/18
- IPC: H04N7/18

Abstract:
A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.
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