Invention Grant
- Patent Title: Method of forming fine patterns of semiconductor device
- Patent Title (中): 形成半导体器件精细图案的方法
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Application No.: US11781987Application Date: 2007-07-24
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Publication No.: US08026044B2Publication Date: 2011-09-27
- Inventor: Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Pan-suk Kwak , Min-jong Hong
- Applicant: Doo-youl Lee , Han-ku Cho , Suk-joo Lee , Gi-sung Yeo , Pan-suk Kwak , Min-jong Hong
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2007-0020574 20070228
- Main IPC: G03F7/00
- IPC: G03F7/00 ; G03F7/004 ; G03F7/20 ; G03F7/26 ; G03F7/40

Abstract:
A method of forming fine patterns on a semiconductor substrate includes forming a first pattern, including first line patterns having a feature size F and an arbitrary pitch P, and forming a second pattern, including second line patterns disposed between adjacent first line patterns, to form a fine pattern having a half pitch P/2, the first and second line patterns being repeated in the first direction. A gap is formed in at least one first line pattern in a second direction, perpendicular to the first direction, to connect second line patterns positioned on each side of the first line pattern through the gap. At least one jog pattern, extending in the first direction, is formed from at least one first line pattern adjacent to the connected second line patterns. The jog pattern causes a gap in at least one of the connected second line patterns in the second direction.
Public/Granted literature
- US20080206686A1 METHOD OF FORMING FINE PATTERNS OF SEMICONDUCTOR DEVICE Public/Granted day:2008-08-28
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