发明授权
- 专利标题: Interconnect structures comprising capping layers with low dielectric constants and methods of making the same
- 专利标题(中): 互连结构包括具有低介电常数的封端层及其制造方法
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申请号: US12190131申请日: 2008-08-12
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公开(公告)号: US08026166B2公开(公告)日: 2011-09-27
- 发明人: Griselda Bonilla , Tien Cheng , Lawrence A. Clevenger , Stephan Grunow , Chao-Kun Hu , Roger A. Quon , Zhiguo Sun , Wei-tsui Tseng , Yiheng Xu , Yun Wang , Hyeok-sang Oh
- 申请人: Griselda Bonilla , Tien Cheng , Lawrence A. Clevenger , Stephan Grunow , Chao-Kun Hu , Roger A. Quon , Zhiguo Sun , Wei-tsui Tseng , Yiheng Xu , Yun Wang , Hyeok-sang Oh
- 申请人地址: US NY Armonk KR SG Singapore
- 专利权人: International Business Machines Corporation,Samsung Electronics Co., Ltd.,Chartered Semiconductor Manufacturing Ltd.
- 当前专利权人: International Business Machines Corporation,Samsung Electronics Co., Ltd.,Chartered Semiconductor Manufacturing Ltd.
- 当前专利权人地址: US NY Armonk KR SG Singapore
- 代理机构: Cantor Colburn LLP
- 代理商 Yuanmin Cai
- 主分类号: H01L21/4763
- IPC分类号: H01L21/4763
摘要:
Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.