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US08026749B2 Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit 失效
锁相环电路，锁相环电路的操作方法和包括锁相环电路的半导体存储器件

Phase locked loop circuit, method of operating phase locked loop circuit and semiconductor memory device including phase locked loop circuit
摘要：
A phase locked loop circuit includes a delay compensation circuit and a phase change circuit. The delay compensation circuit is adapted to generate a delay clock signal by delaying a phase of a first output clock signal by a second phase, the phase of the first output clock signal having a phase leading a phase of an input clock signal by a first phase, and the second phase corresponding to a delay compensation time greater than a period of the input clock signal and greater than the first phase. The phase change circuit is adapted to change the second phase to the first phase and to generate a feedback clock signal having a phase synchronized with the phase of the input clock signal in response to the first phase, wherein the first phase is a phase corresponding to a remainder time resulting from the delay compensation time being divided by the period of the input clock, and wherein the quotient is an integer.
摘要（中）：

锁相环电路包括延迟补偿电路和相变电路。 延迟补偿电路适于通过将第一输出时钟信号的相位延迟第二相来产生延迟时钟信号，第一输出时钟信号的相位具有将输入时钟信号的相位引导到第一相位的相位 ，并且第二相位对应于大于输入时钟信号的周期的延迟补偿时间并且大于第一相位。 相变电路适于将第二相位改变为第一相位，并响应于第一相位产生具有与输入时钟信号的相位同步的相位的反馈时钟信号，其中第一相位是对应于 由延迟补偿时间产生的剩余时间除以输入时钟的周期，并且其中商是整数。

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