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发明授权
US08031015B2 Phase-locked loop circuit 有权
锁相环电路

Phase-locked loop circuit
摘要：
A PLL circuit is disclosed that comprises a controlling unit that switches at a predetermined timing to enable/disable the phase difference signal supplied from the phase comparator to the low pass filter; and a resistor element that is disposed between a predetermined potential and a signal line for supplying the phase difference signal from the phase comparator to the low pass filter, when the phase difference signal is enabled, the oscillation circuit performing oscillation operation based on the voltage signal corresponding to the phase difference signal, when the phase difference signal is disabled, the low pass filter being supplied with the predetermined potential through the resistor element to allow the oscillation circuit to perform oscillation operation based on the voltage signal generated depending on the supplied predetermined potential.
摘要（中）：

公开了一种PLL电路，其包括控制单元，其在预定定时切换以使得能够/禁止从相位比较器提供给低通滤波器的相位差信号; 以及电阻元件，其设置在用于将相位差信号从相位比较器提供给低通滤波器的预定电位和信号线之间，当相位差信号有效时，振荡电路根据电压信号进行振荡运算 对应于相位差信号，当相位差信号被禁止时，低通滤波器通过电阻元件被提供预定电位，以允许振荡电路根据所提供的预定电位产生的电压信号进行振荡操作 。

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